Microchip Technology /ATSAMV71N21B /USBHS /DEVEPTIMR_ISO_MODE[6]

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Interpret as DEVEPTIMR_ISO_MODE[6]

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TXINE)TXINE 0 (RXOUTE)RXOUTE 0 (UNDERFE)UNDERFE 0 (HBISOINERRE)HBISOINERRE 0 (HBISOFLUSHE)HBISOFLUSHE 0 (OVERFE)OVERFE 0 (CRCERRE)CRCERRE 0 (SHORTPACKETE)SHORTPACKETE 0 (MDATAE)MDATAE 0 (DATAXE)DATAXE 0 (ERRORTRANSE)ERRORTRANSE 0 (NBUSYBKE)NBUSYBKE 0 (KILLBK)KILLBK 0 (FIFOCON)FIFOCON 0 (EPDISHDMA)EPDISHDMA 0 (RSTDT)RSTDT

Description

Device Endpoint Interrupt Mask Register

Fields

TXINE

Transmitted IN Data Interrupt

RXOUTE

Received OUT Data Interrupt

UNDERFE

Underflow Interrupt

HBISOINERRE

High Bandwidth Isochronous IN Underflow Error Interrupt

HBISOFLUSHE

High Bandwidth Isochronous IN Flush Interrupt

OVERFE

Overflow Interrupt

CRCERRE

CRC Error Interrupt

SHORTPACKETE

Short Packet Interrupt

MDATAE

MData Interrupt

DATAXE

DataX Interrupt

ERRORTRANSE

Transaction Error Interrupt

NBUSYBKE

Number of Busy Banks Interrupt

KILLBK

Kill IN Bank

FIFOCON

FIFO Control

EPDISHDMA

Endpoint Interrupts Disable HDMA Request

RSTDT

Reset Data Toggle

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